The preferred embodiments relate to testing of integrated circuits and, more particularly, to improved test data throughput with usage of all JTAG pins.
Various techniques have been created, modified, and have evolved for testing functional cores, including logic and memories, and other circuits on an integrated circuit (IC), or multiple ICs on a printed circuit board (PCB). The older “bed of nails” testing techniques had limitations, particularly as a result of increasing larger-scales, greater complexity, and inaccessible nodes in ICs, and also in view of densely packed multilayer PCBs. As a result, contemporary testing is often more (or fully) automated and typically involves inputting data to an IC, executing one or more clock cycles on the input data, and then capturing and outputting the result, where the results can then be analyzed, such as by comparing them to an anticipated result where such comparison either thereby verifies proper operation or detects improper operation. Such testing in part arose from findings and recommendations of a Joint Test Action Group (JTAG) formed of various silicon manufacturers, which were then used as a basis for the IEEE standard 1149.1 and subsequent versions thereof. With this standard and these developments, many contemporaries ICs include some level of embedded circuitry and an input/output interface to facilitate testing. Under 1149.1, also referred to as JTAG given its origination, four or five pins are included on an IC, each corresponding to a respective dedicated test access port (TAP) signal for testing interconnects on either the IC or a PCB into which the IC is assembled. Specifically, the TAP signals may be used to determine whether an IC is properly functioning, whether it is connected to the PCB, and also for debugging by observing IC pin states or measured voltages. Testing may be achieved at the time of manufacture, such as by automated testing equipment (ATE), as well as subsequent testing in the field (e.g., once a device has been sold or located in the marketplace). Additional details are specified in IEEE 1149 and its .x sub-standards.
By way of further background, FIG. 1 illustrates an electrical block diagram of an IC 10 having a JTAG architecture according to the prior art, and which further includes boundary scanning, although certain designs may include JTAG without boundary scanning. For purposes of simplification, IC 10 is shown to include a test access port TAP controller 12 for interfacing with TAP signals and as relating to JTAG testing. IC 10 also includes functional circuitry 14, sometimes referred to as a core, which is a general depiction of the various circuit functions of IC 10 including ALU, processing circuitry, logic, memories and the like, apart from JTAG testing. IC 10 also includes a number of I/O pins (sometimes also called pads) P0 through P15, shown at various locations around the perimeter of the device. Pins P0 through P4 carry respective and known JTAG TAP related signals, as shown in the following Table 1.
TABLE 1PinJTAG SignalFunctionP0TDOtest data outP1TRSTtest resetP2TMStest mode selectP3TCKtest clockP4TDItest data inAs indicated in Table 1, pin P4 allows input of JTAG test data and pin P0 allows output thereof, while the remaining pins P1 through P3 provide respective signals to TAP controller 12. An instruction register 16 stores a current JTAG instruction, typically to indicate the operation to take with respect to signals that are received (e.g., defining to which data register signals should pass). A bypass register 18 is a single bit register that permits TDI to bypass a boundary scan chain of individual serially connected registers, typically comprising one or more flip flops, referred to herein as cells C0 through C15, so as to pass directly from input to output. An ID register 20 is for storing the ID code and revision number for IC 10, thereby allowing IC 10 to be linked to a file that stores boundary scan configuration information for IC 10.
Apart from the JTAG-related pins P0 through P4, each of the remaining IC pins P5 through P15 is connected to respective boundary scan cell C5 through C15, where each such cell can transfer data in two manners, the first being able to pass cell data received from its respective pin, through the cell, to functional circuitry 14; and the second being along the chain of cells C5 through C15. Thus, in the first manner of data transfer, such pins represent the bidirectional I/O of IC 10, in connection with its intended operation as achieved by functional circuitry 14, in which case the cells are effectively transparent. In the second manner of data transfer, however, which also is in connection with JTAG testing, each of scan cells C5 through C15 is connected to at least one other scan cell and is operable to shift data from itself to that connected cell, thereby forming a boundary scan chain whereby for JTAG purposes data may be input by a respective pin to each cell, or captured in each cell from functional circuitry 14, and then such data may be successively shifted along the chain in a direction from lower numbered toward higher numbered cells, so that test data ultimately is output from the last such cell C15 as TDO information. In this manner, therefore, the I/O connectivity as well as data states from functional circuitry 14 may be evaluated so as to confirm proper operation of IC 10.
Scan testing is not limited to boundary scans using JTAG. Some ICs include additional and non-boundary or internal chains of cells (registers) sometimes referred to as stumps (or STUMPS—self-testing using MISR [multiple input signature register] and parallel SRSG [shift register sequence generator]). In this context, data is input to the IC across numerous pins and then distributed to the one or more internal scan chains, where again one or more execution cycles are performed and then the results are captured into the scan chain(s) and output from the device. To accomplish such testing, typically the input test data may involve relatively large quantities representing considerable testing time and other resources, so these test sets may be reduced and input to the IC, then decompressed into a larger data set for testing; moreover, after the test execution cycle(s), the result is then compressed prior to outputting the counterpart result data. While such an approach has various benefits, it also is limited, for example, in ICs having a relatively low pin count, as the reduced number of pins constrains the amount of test data that may be input to the IC, or output from the IC, at a time. Additional prior art approaches, therefore, have arisen to address these constrains, but they typically still present some penalty in terms of test time. Moreover, some such approaches are only suitable where the number of scan inputs required is very high, whereas for many modern ICs this requirement may not be the case, or the needs given the IC and testing requirements could be better addressed with other approaches, were such approaches available in the art.
Also in the prior art certain JTAG pins are sometimes used for purposes other than JTAG data or JTAG TAP control. For example, in one prior art approach, the TMS pin may be used first as a control to the tap controller 12 so as to place the JTAG finite state machine (FSM) into one of its 16 states, namely, the Run-Test/Idle state, wherein the FSM either remains idle or, upon reaching the state the TMS pin is released while a scan test is then performed. In this approach, however, once the test is complete, if an alternative test is desired, the formerly released TMS pin is no longer available for controlling the TAP controller FSM; instead, under the prior art, a power-on-reset (PoR) is required, which typically defines a time that at least some functional portion of the IC is placed in a reset state, as may be defined for example by the RC constant of a resistor and capacitor. In any event, during this reset state, at least portions of the IC functionality are not operable for input/output and other operation, while instead the supply voltage is allowed sufficient time, and the rest of the states of the device are restored, to a known start-up state. Thus, for each such repeated instance of the released TMS pin followed by a test and a PoR, then valuable time is consumed and thereby added to the overall testing time, for each successive PoR event. Indeed, in contemporary devices, a PoR cycle can result in an overhead of 100 ms per PoR event, so multiple successive releases of the TMS pin considerably add to test time. As an alternative, the TMS pin may be reserved at all times solely to provide control to the TAP controller, but such an approach therefore eliminates the TMS pin as a candidate for providing test data, in which case there is considerably greater overhead in reducing the amount of test data that can be input to the IC, without the use of this pin.
Given the preceding, the prior art poses various complexities and drawbacks, and the preferred embodiments provide a favorable alternative, as further detailed below.